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`!eSi-RISC`! is a configurable `F33f`_`[CPU`:/page/wikibook/entry.mu`zim=wikipedia_en_all_nopic_2025-08.zim|entry_path=CPU]`_`f architecture. It is available in five implementations: the eSi-1600, eSi-1650, eSi-3200, eSi-3250 and eSi-3264.`:cite-ref-1[`F5bf`_`[1`#cite-note-1]`_`f] The eSi-1600 and eSi-1650 feature a `F33f`_`[16-bit`:/page/wikibook/entry.mu`zim=wikipedia_en_all_nopic_2025-08.zim|entry_path=16-bit]`_`f data-path, while the eSi-32x0s feature `F33f`_`[32-bit`:/page/wikibook/entry.mu`zim=wikipedia_en_all_nopic_2025-08.zim|entry_path=32-bit]`_`f data-paths, and the eSi-3264 features a mixed 32/64-bit datapath. Each of these processors is licensed as soft `F33f`_`[IP cores`:/page/wikibook/entry.mu`zim=wikipedia_en_all_nopic_2025-08.zim|entry_path=IP_core]`_`f, suitable for integrating into both `F33f`_`[ASICs`:/page/wikibook/entry.mu`zim=wikipedia_en_all_nopic_2025-08.zim|entry_path=Application-specific_integrated_circuit]`_`f and `F33f`_`[FPGAs`:/page/wikibook/entry.mu`zim=wikipedia_en_all_nopic_2025-08.zim|entry_path=FPGA]`_`f.`:cite-ref-2[`F5bf`_`[2`#cite-note-2]`_`f]

>>Contents

• `F0af`_`[Architecture`#architecture]`_`f

• `F0af`_`[Toolchain`#toolchain]`_`f

• `F0af`_`[References`#references]`_`f

• `F0af`_`[External links`#external-links]`_`f

-─

>>Architecture

The main features of the eSi-RISC architecture are:`:cite-ref-3[`F5bf`_`[3`#cite-note-3]`_`f]

• `F33f`_`[RISC`:/page/wikibook/entry.mu`zim=wikipedia_en_all_nopic_2025-08.zim|entry_path=RISC]`_`f-like load/store architecture.

• Configurable 16-bit, 32-bit or 32/64-bit data-path.

• Instructions are encoded in either 16 or 32-bits.

• 8, 16 or 32 general purpose registers, that are either 16 or 32-bits wide.

• 0, 8, 16 or 32 vector registers, that are either 32 or 64-bits wide.

• Up to 32 external, vectored, nested and prioritizable interrupts.

• Configurable instruction set including support for integer, floating-point and fixed-point arithmetic.

• `F33f`_`[SIMD`:/page/wikibook/entry.mu`zim=wikipedia_en_all_nopic_2025-08.zim|entry_path=SIMD]`_`f operations.

• Optional support for user-defined instructions, such as cryptographic acceleration .`:cite-ref-4[`F5bf`_`[4`#cite-note-4]`_`f]

• Optional caches (Configurable size and associativity).

• Optional `F33f`_`[MMU`:/page/wikibook/entry.mu`zim=wikipedia_en_all_nopic_2025-08.zim|entry_path=Memory_management_unit]`_`f supporting both memory protection and dynamic address translation.

• `F33f`_`[AMBA`:/page/wikibook/entry.mu`zim=wikipedia_en_all_nopic_2025-08.zim|entry_path=Advanced_Microcontroller_Bus_Architecture]`_`f AXI, AHB and APB bus interfaces.

• Memory mapped I/O.

• 5-stage pipeline.

• Hardware `F33f`_`[JTAG`:/page/wikibook/entry.mu`zim=wikipedia_en_all_nopic_2025-08.zim|entry_path=JTAG]`_`f debug.

While there are many different 16 or 32-bit `F33f`_`[Soft microprocessor`:/page/wikibook/entry.mu`zim=wikipedia_en_all_nopic_2025-08.zim|entry_path=Soft_microprocessor]`_`f IP cores available, eSi-RISC is the only architecture licensed as an IP core that has both 16 and 32-bit implementations.

Unlike in other RISC architectures supporting both 16 and 32-bit instructions, such as ARM/Thumb or MIPS/MIPS-16, 16 and 32-bit instructions in the eSi-RISC architecture can be freely intermixed, rather than having different modes where either all 16-bit instructions or all 32-bit instructions are executed. This improves code density without compromising performance. The 16-bit instructions support two register operands in the lower 16 registers, whereas the 32-bit instructions support three register operands and access to all 32 registers.

eSi-RISC includes support for `F33f`_`[Multiprocessing`:/page/wikibook/entry.mu`zim=wikipedia_en_all_nopic_2025-08.zim|entry_path=Multiprocessing]`_`f. Implementations have included up to seven eSi-3250's on a single chip.`:cite-ref-5[`F5bf`_`[5`#cite-note-5]`_`f]

>>Toolchain

The eSi-RISC toolchain is based on combination of a port of the `F33f`_`[GNU toolchain`:/page/wikibook/entry.mu`zim=wikipedia_en_all_nopic_2025-08.zim|entry_path=GNU_toolchain]`_`f and the `F33f`_`[Eclipse`:/page/wikibook/entry.mu`zim=wikipedia_en_all_nopic_2025-08.zim|entry_path=Eclipse_ide]`_`f `F33f`_`[IDE`:/page/wikibook/entry.mu`zim=wikipedia_en_all_nopic_2025-08.zim|entry_path=Integrated_development_environment]`_`f.`:cite-ref-6[`F5bf`_`[6`#cite-note-6]`_`f] This includes:

• `F33f`_`[GCC`:/page/wikibook/entry.mu`zim=wikipedia_en_all_nopic_2025-08.zim|entry_path=GNU_Compiler_Collection]`_`f – C/C++ compiler.

• `F33f`_`[Binutils`:/page/wikibook/entry.mu`zim=wikipedia_en_all_nopic_2025-08.zim|entry_path=Binutils]`_`f – Assembler, linker and binary utilities.

• `F33f`_`[GDB`:/page/wikibook/entry.mu`zim=wikipedia_en_all_nopic_2025-08.zim|entry_path=GDB]`_`f – Debugger.

• `F33f`_`[Eclipse`:/page/wikibook/entry.mu`zim=wikipedia_en_all_nopic_2025-08.zim|entry_path=Eclipse_ide]`_`f – Integrated Development Environment.

The C library is `F33f`_`[Newlib`:/page/wikibook/entry.mu`zim=wikipedia_en_all_nopic_2025-08.zim|entry_path=Newlib]`_`f and the C++ library is `F33f`_`[Libstdc++`:/page/wikibook/entry.mu`zim=wikipedia_en_all_nopic_2025-08.zim|entry_path=Libstdc++]`_`f. Ported `F33f`_`[RTOSes`:/page/wikibook/entry.mu`zim=wikipedia_en_all_nopic_2025-08.zim|entry_path=RTOS]`_`f include `F33f`_`[MicroC/OS-II`:/page/wikibook/entry.mu`zim=wikipedia_en_all_nopic_2025-08.zim|entry_path=MicroC/OS-II]`_`f, `F33f`_`[FreeRTOS`:/page/wikibook/entry.mu`zim=wikipedia_en_all_nopic_2025-08.zim|entry_path=FreeRTOS]`_`f, `F33f`_`[ERIKA Enterprise`:/page/wikibook/entry.mu`zim=wikipedia_en_all_nopic_2025-08.zim|entry_path=ERIKA_Enterprise]`_`f`:cite-ref-7[`F5bf`_`[7`#cite-note-7]`_`f] and `F33f`_`[Phoenix-RTOS`:/page/wikibook/entry.mu`zim=wikipedia_en_all_nopic_2025-08.zim|entry_path=Phoenix-RTOS]`_`f`:cite-ref-8[`F5bf`_`[8`#cite-note-8]`_`f]

>>References

`:cite-note-1`!1.`! `F0af`_`[↑`#cite-ref-1]`_`f [1] Electronics Weekly, 17 November 2009

`:cite-note-2`!2.`! `F0af`_`[↑`#cite-ref-2]`_`f [2] EE Times, 17 November 2009

`:cite-note-3`!3.`! `F0af`_`[↑`#cite-ref-3]`_`f [3] eSi-RISC eSi-3250 Technical Overview

`:cite-note-4`!4.`! `F0af`_`[↑`#cite-ref-4]`_`f [4] Electronics Weekly, 2013

`:cite-note-5`!5.`! `F0af`_`[↑`#cite-ref-5]`_`f [5] Design & Reuse, 2011

`:cite-note-6`!6.`! `F0af`_`[↑`#cite-ref-6]`_`f [6] Archived 28 February 2012 at the `F33f`_`[Wayback Machine`:/page/wikibook/entry.mu`zim=wikipedia_en_all_nopic_2025-08.zim|entry_path=Wayback_Machine]`_`f EnSilica, 2009

`:cite-note-7`!7.`! `F0af`_`[↑`#cite-ref-7]`_`f [7] Electronics Weekly, 2010,

`:cite-note-8`!8.`! `F0af`_`[↑`#cite-ref-8]`_`f [8] Cambridge Network 2013

>>External links

• eSi-RISC homepage

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